Difference between revisions of "MLU Programming"

Revision as of 14:28, 12 February 2014

The CAEN 1495 is programmed as an MLU to form triggers.

Picture:

http://userweb.jlab.org/~rom/mlu.xfig.png

  MLU programming.  
  Feb 5 2014    R. Michaels 

  Note, channel #1 is at the bottom.

  There are 3 inputs
     A and B - 32 chan ECL -- to be ignored
     E - 8 chan NIM  -- to be used

  There are 3 outputs
     C - 32 chan LVDS  (converted to ECL with another board)
     F - 8 chan NIM

               A ||
                 ||
               
               B ||  * E   NIM input
                 ||  *
 
   LVDS output C ||  * F   NIM output
                 ||  *


  The outputs are arranged so that (with indices starting at 1):
       C(1-8), C(9-16), C(17-23), C(24-32), and F(1-8)
  are identical.
  This provides 5 copies of the trigger signals.

    Inputs on E 
       1. S0   scintillator
       2. S2   scintillator
       3. GC   gas cherenkov
       4. SH   shower
       5. EDTM
       6. Clock

  Default programming desired by GMp  (per Bogdan W.)

     Outputs
       1. S0 & S2   (logical "and")
       2. S0 & GC
       3. S2 & GC
       4. S0 & SH
       5. S2 & SH
       6. GC & SH
       7. EDTM 
       8. Clock 

  Alternative MLU -- software selectable.
     (normally not used, but might be used by DVCS)

     Outputs
       1. S0 
       2. S0 
       3. GC
       4. SH
       5. S0 || S2
       6. (S0 & S2) || (S0 & GC) || (S2 & GC)    2/3 trigger
       7. EDTM 
       8. Clock 

Here are some notes from testing the setup in the TEDF building. The MLU will be deployed on the L-HRS. We'll need to obtain more CAEN 1495 boards to instrument the R-HRS

   Notes from testing

       The ECL outputs 7 and 8 are flipped polarity.
       This could affect some timing.

       All the NIM outputs have appropriate polarity.

       For the LVDS to ECL converter I have, 4 channels are bad
       (index starting at 1):  7, 9, 23, and 32.
       We'll also need to ask for more converters.
       
       Input pin #8 on the NIM mezzanine E is broken.
       We don't use it, though.  We should get spare cards.

       The delay through the 1495 to NIM output is 20 nsec.
       The logic follows the timing of the inputs.  Jitter 
       is negligible.

       If the power is turned off
         -- the FPGA programming is preserved
         -- but the module must be initialized with 
            software, or there is no output.
 
       We will arrange to initialize the MLU with software 
       whenever the VME board is rebooted.