Difference between revisions of "MLU Programming"

Revision as of 15:18, 1 May 2014

The CAEN 1495 is programmed as an MLU to form triggers.

Picture of MLU

http://userweb.jlab.org/~rom/mlu.xfig.png

GUI used for control

Picture

http://userweb.jlab.org/~rom/mlugui.png

Instructions: Login to "atrig" an adaq computer and type "trigsetup". The GUI is obvious but if you need help press "HELP" on it for more info.

Some related technical info follows

The MLUs are CAEN 1495 boards with specific FPGA programming (explained below) deployed on both the L-HRS and R-HRS. The MLUs are set up by VME-based IntelPCs: on L-HRS it is intelha3 and on the R-HRS it is halladaq8. All the following instructions work for both MLUs.

The trigsetup GUI invokes scripts on the intel PCs.

New as of April 15, 2014: the outputs can be disabled. This is fairly obvious with both "trigsetup" GUI.

When that PC reboots it puts the MLU into the state defined in /root/mlu/modefile. The code /mlu/initmlu which writes to the mlu is invoked. This code is also called every 4 minutes under cron, just to ensure that the MLU is always in the right state (does no harm). Finally, the code is called when the PC reboots, using an entry in /etc/rc.local The trigsetup GUI interacts with the MLU by talking to a server which writes to /root/mlu/modefile and then does a system call to invoke /mlu/initmlu

Programming Details

  MLU programming.  
  Feb 5 2014    R. Michaels 

  Note, channel #1 is at the bottom.

  There are 3 inputs
     A and B - 32 chan ECL -- to be ignored
     E - 8 chan NIM  -- to be used

  There are 3 outputs
     C - 32 chan LVDS  (converted to ECL with another board)
     F - 8 chan NIM

               A ||
                 ||
               
               B ||  * E   NIM input
                 ||  *
 
   LVDS output C ||  * F   NIM output
                 ||  *


  The outputs are arranged so that (with indices starting at 1):
       C(1-8), C(9-16), C(17-23), C(24-32), and F(1-8)
  are identical.
  This provides 5 copies of the trigger signals.

    Inputs on E 
       1. S0   scintillator
       2. S2   scintillator
       3. GC   gas cherenkov
       4. SH   shower
       5. EDTM
       6. Clock

 

GMp Standard Triggers

     Outputs
       1. S0 & S2   (logical "and")
       2. S0 & GC
       3. S2 & GC
       4. S0 & SH
       5. S2 & SH
       6. GC & SH
       7. EDTM 
       8. Clock 

Single Detector Triggers   and other triggers

  Single Detector Triggers -- Alternative MLU -- software selectable.
     (normally not used, but might be used by DVCS)

     Outputs
       1. S0 
       2. S2 
       3. GC
       4. SH
       5. S0 || S2
       6. (S0 & S2) || (S0 & GC) || (S2 & GC)    2/3 trigger
       7. EDTM 
       8. Clock 

Notes from Testing

Here are some notes from testing the setup in the TEDF building.

   Notes from testing

       All the NIM outputs have appropriate polarity.
       One must take care to select the jumpers so that NIM inputs
       have 50 ohm termination -- otherwise you get reflections.
       There were a couple channels that didn't have 50 ohm even
       with the jumpers set right; Bill Gunning fixed it.

       The ECL outputs 7 and 8 are flipped polarity.
       This could affect some timing.

       For the LVDS to ECL converter I have, 4 channels were bad
       (index starting at 1):  7, 9, 23, and 32.
       We'll also need to ask for more converters.
       
       Input pin #8 on the NIM mezzanine E is broken on L-HRS MLU.
       We don't use it, though.  We should get spare cards.

       The delay through the 1495 to NIM output is 20 nsec.
       The logic follows the timing of the inputs.  Jitter 
       is negligible.

       If the power is turned off
         -- the FPGA programming is preserved
         -- but the module must be initialized with 
            software, or there is no output.
 
       We have arranged to initialize the MLU with software 
       whenever the VME board is rebooted.