Difference between revisions of "Trigger"

Revision as of 12:45, 3 November 2014

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Trigger configuration

That file is kept under dvcs@intelhadvcs1:~/config_files

1. 1. Example configuration file

Global Threshold = 750 Cluster Threshold = 250 Require Cluster = 0

1. Gate width setting is in increments of 5ns

Gate Width = 14

2. Prescale settings are in powers of two:
3. ___Behavior__________ Setting
4. PRESCALE_VAL_DISABLED 0
5. PRESCALE_VAL_NONE 1
6. PRESCALE_VAL_2 2
7. PRESCALE_VAL_4 3
8. PRESCALE_VAL_8 4
9. PRESCALE_VAL_16 5
10. PRESCALE_VAL_32 6
11. PRESCALE_VAL_64 7
12. PRESCALE_VAL_128 8
13. PRESCALE_VAL_256 9
14. PRESCALE_VAL_512 10
15. PRESCALE_VAL_1024 11
16. PRESCALE_VAL_2048 12
17. PRESCALE_VAL_4096 13
18. PRESCALE_VAL_8192 14
19. PRESCALE_VAL_16384 15
20. Prescale channel assignments are:
21. PRESCALE_ID_CLOCK 0
22. PRESCALE_ID_COSMIC 1
23. PRESCALE_ID_S2M_NCER 2
24. PRESCALE_ID_S0_S1 3
25. PRESCALE_ID_S0_S2M 4
26. PRESCALE_ID_S0_CER 5
27. PRESCALE_ID_S1_S2M 6
28. PRESCALE_ID_S1_CER 7
29. PRESCALE_ID_S2M_CER 8

Prescale_0 Clock = 0 Prescale_1 Cosmic = 0 Prescale_2 S2M and NCER = 1 Prescale_3 S0 and S1 = 0 Prescale_4 S0 and S2M = 0 Prescale_5 S0 and CER = 0 Prescale_6 S1 and S2M = 0 Prescale_7 S1 and CER = 0 Prescale_8 S2M and CER = 1

BEGIN_PEDESTALS

1. Data1 Pedestals:

2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 001-008 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 009-016 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 017-024 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 025-032 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 033-040 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 041-048 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 049-056 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 057-064 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 065-072 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 073-080

1. Data2 Pedestals:

2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 081-088 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 089-096 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 097-104 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 105-112 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 113-120 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 121-128 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 129-136 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 137-144

1. Data3 Pedestals:

2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 145-152 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 153-160 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 161-168 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 169-176 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 177-184 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 185-192 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 193-200 2048 2048 2048 2048 2048 2048 2048 2048 # Hardware channels 201-208

END_PEDESTALS

Trigger patterns

Trigger patterns: The lowest six bits of the triggerPattern word (mask value=0x3f) record the status of the raw trigger inputs. Depending on the prescale settings, a trigger input may be present even if it was not included in the event trigger for that event.

The remainder of the bits (mask value=0xffffff40) record which prescaled coincidence trigger was actually used to form the event trigger.

Documentation

• [Readiness Review Report (September 2014)]
• [Electronic Review document (May 2014)]
• [Trigger Manual (May 2014)] [Trigger Manual (Sept 2013)]
• [Trigger upgrade talk (March 2011)]