Difference between revisions of "DVCS DAQ Oct 18th"
From Hall A Wiki
| Line 8: | Line 8: | ||
Issues : | Issues : | ||
| − | *ARS empty FIFO message and synchronization | + | *ARS empty FIFO message and synchronization [[http://www.jlab.org/~adaq/halog/html/1010_archive/101018011154.html]] |
*data still shifts in the buffer | *data still shifts in the buffer | ||
*ARS initialization - not clear if we start shifted by one | *ARS initialization - not clear if we start shifted by one | ||
Latest revision as of 08:54, 18 October 2010
Status :
- Top crate works ok
- move to other crate improved : can take full calorimeter data
- trigger read out, firmware being checked - test during access
- data with issues but most likely good enough for elastic calibration
- still need to validate some components for cross sections measurement
Issues :
- ARS empty FIFO message and synchronization [[1]]
- data still shifts in the buffer
- ARS initialization - not clear if we start shifted by one
- spares : no spare left - one crashing - one loosing synch
Requirements for production :
- now
- check ARS mapping with calorimeter
- Dead time calculation
- sync check
- helicity
- ARS trigger efficiency - data taking efficiency
- calorimeter calibration
- short term
- trigger
- logic module with triggers and bit pattern, on board scaler for dead time
Data to be analyzed :
- elastic data
- sync data
- optics data
- BCM calibration
- Pion rejector calibration
Possible plan :
- today
- During access :
- check trigger
- test sync checks, scalers, dead time
- trigger power cycling
- EPICS crate - HV cratea power cycling
- ARS mapping check with LED
- Meeting with DAQ/ Electronics group at 2 PM room F227
- During access :
- continue elastic calibration Monday owl, update ARS firmware
- Tuesday, Wednesday - trigger commissioning
- polarity change Thursday - take DVCS production single and coincidence - check consistency between S2 trigger and S2 trigger in logic module - Question stay at 5 pass or go to lower pass ?
