Trigger
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Trigger patterns
Trigger patterns: The lowest six bits of the triggerPattern word (mask value=0x3f) record the status of the raw trigger inputs. Depending on the prescale settings, a trigger input may be present even if it was not included in the event trigger for that event.
| Trigger input | Bit pattern | Value |
| COSMIC | 0x00001 | 1 |
| TRIGCLK | 0x00002 | 2 |
| SO | 0x00004 | 4 |
| S1 | 0x00008 | 8 |
| S2M | 0x00010 | 16 |
| CER | 0x00020 | 32 |
The remainder of the bits (mask value=0xffffff40) record which prescaled coincidence trigger was actually used to form the event trigger.
| Event trigger | Bit pattern | Value |
| S2M_NCER_SCALED | 0x00040 | 64 |
| S2M_CER2_SCALED | 0x00080 | 128 |
| S2M_CER_SCALED | 0x00100 | 256 |
| S1_CER_SCALED | 0x00200 | 512 |
| S1_S2M_SCALED | 0x00400 | 1024 |
| S0_CER_SCALED | 0x00800 | 2048 |
| S0_S2M_SCALED | 0x01000 | 4096 |
| S0_S1_SCALED | 0x02000 | 8192 |
| TRIG_VME | 0x04000 | 16384 |
| COSMIC_SCALED | 0x08000 | 32768 |
| TRIGCLK_SCALED | 0x10000 | 65536 |
