FADC DAQ V2 2018

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Documentation

NOTE: This page under development!!!

DAQ V2

FADC Documentation

Test FADC V2

SBS DAQ VME computer (Linux, Intel CPU) "sbsvme22" and PC computer "sbs1" located in TestLab have been used for testing a new FADC V2.
PC computer is used to run CODA.
Original software and library from CODA group are located in /site/coda/contrib/devel/halla_moller/
We have copy of this directory to sbsvme22 computer in "~/git/" directory. FADC configured to use internal helicity generator with frequency set to 30Hz.

Testing FADC with CODA

Login to VME CPU (password from Alex or Bob): 
> ssh root@sbsvme22
go to moller fadc directory:
> cd git/halla_moller/
Start CODA ROC manually
> coda_roc_rc3.5 -name TS1 -type ROC
Original CODA readout list is: ~/git/halla_moller/fadc/moller_rol/moller_list.c
CODA readout list with FADC parameters from configuration file is: ~/git/halla_moller/fadc/moller_rol/test_moller_list.c
To compile readout list:
> cd ~/git/halla_moller/fadc/moller_rol/
> make test_moller_list.so
Change readout list in database:
> dbedit
select "sbsfb" database,
select "MollerFADC" table,
change readout list in "TS1-code" cell,
exit from dbedit.
Login to sbs1 computer (password from Alex or Bob): 
> ssh adaq@sbs1
Type in terminal:
> startcoda
Select session sbsfb1 and configuration MollerFADC
CODA files are stored to directory: ~adaq/data/moller_NN.dat
Configuration file with FADC parameters is located in:
 sbsvme22:~/git/halla_moller/fadc/moller_rol/config_1.fadc
Configuration file "config_1.fadc":
# Fri Feb 16 14:39:26 EST 2018
# FADC-V2 settable parameters
# All delays are set to aligne signals in History FiFo

# Threshold on calorimeter sums (define triggers and SW scaler logic)
# These thresholds are independed  from FA_THRESH_CAL
FA_SUM_THRESH_CR   1000
FA_SUM_THRESH_CL   1000
# Threshold on all calorimeter and scintilator channels (for PLU with scalers)
# These thresholds are independed  from FA_SUM_THRESH_CL
FA_THRESH_CAL      500
FA_THRESH_SCINT    500

# Threshold on individual channels 
#   Define SW scaler logic for Scintillators only 
#   Controls digitized data output for all channels (ie. 'zero-suppression')
#   only FA_CHN_THRESH_CL is used now
FA_CHN_THRESH_CL     400
FA_CHN_THRESH_CR     400
FA_CHN_THRESH_SR     400
FA_CHN_THRESH_SL     400
## Prescale range: 1--2047; 0- disable  data trigger 
FADC_PRESCALE_CL   1
FADC_PRESCALE_CR   1
FADC_PRESCALE_CRL  1 

## These many DATA trigger are grouped into each DATA interrupt
FADC_EVENTS_PER_BLOCK 10 

## PULSE_WIDTH range is from 3--255 (3 is default, 0=4ns)
FADC_PULSE_WIDTH  3
FADC_SUM_PULSE_WIDTH  3

## COIN_WIDTH range is from 1--255  (2 is default)
FADC_COIN_WINDOW  4 

## Delays range: 1--255
FADC_DELAY_CL     2
FADC_DELAY_CR     2
FADC_DELAY_SL_0   7
FADC_DELAY_SL_1   7
FADC_DELAY_SL_2   7
FADC_DELAY_SL_3   7
FADC_DELAY_SR_0   7
FADC_DELAY_SR_1   7
FADC_DELAY_SR_2   7
FADC_DELAY_SR_3   7
FADC_DELAY_CL_0   3
FADC_DELAY_CL_1   3
FADC_DELAY_CL_2   3
FADC_DELAY_CL_3   3
FADC_DELAY_CR_0   3
FADC_DELAY_CR_1   3
FADC_DELAY_CR_2   3
FADC_DELAY_CR_3   3
## This delay is for the _delay counts (random background measure)
FADC_DELAY_SRL    25
## PLU registers NOT, AND, OR:
## Name:  NOT_CR1-4  NOT_CL1-4 NOT_SR-SL AND_CR1-4    AND_CL1-4    AND_SR-SL OR_CR1-4     OR_CL1-4     OR_SR-SL
## bits#: 0 1 2 3    4 5 6 7   8 9       10 11 12 13  14 15 16 17  18 19     20 21 22 23  24 25 26 27  28 29
##           SCM-0: CR1*CL1*SL*SR = 0x30004400
FADC_SCM_0   0x30004400
FADC_SCM_1   0x3ff00000
FADC_SCM_2   0x3ff00000
FADC_SCM_3   0x3ff00000
FADC_SCM_4   0x000ffc00
FADC_SCM_5   0x000ffc00
FADC_SCM_6   0x000ffc00
FADC_SCM_7   0x000ffc00 

## PlayBack parameters (in ticks=4ns)
## PB_MODE = 0 playback is OFF; PB_MODE>0 = number of playback triggers (<10)
## (WIDTH+DELAY) must be less then 32 (number of samples for playback is 32)
## PB_SCINT_SIGNAL -  In hexidecimal representation: 
##    signal = (sr_8)(sr_7)(sr_6)(sr_5)(sl_4)(sl_3)(sl_2)(sl_1)
##    nibbles (sl_1)...(sr_8) are the amplitudes (0-F x 100) of a square pulse of duration scint_width
##    riding a top PB_SCINT_PED, starting at sample=PB_SCINT_DELAY
##  Maximum signal is 0x7FFFFFFF
PB_MODE          2
PB_SCINT_PED     200
PB_CAL_PED       100
PB_SCINT_WIDTH   5
PB_CAL_WIDTH     6
PB_SCINT_DELAY   1
PB_CAL_DELAY     1
PB_SCINT_SIGNAL  0x000c000e
PB_CAL_SIGNAL    0x000a000b 
## End of config file

Decoding FADC CODA file

Testing FADC with standalone programs

Login to VME CPU: 
> ssh root@sbsvme22
go to moller fadc test directory:
> cd git/halla_moller/fadc/mytest
FADC can be tested with external signals on inputs ("mode"=0), and with interrnal user defined waveform (PlayBack mode "mode">0).
In PlayBack mode waveforms is defined in configuration file, see file:
~/git/halla_moller/fadc/mytest/config_1.fadc
start readout program:
> ./famFadcTest <config_file_name> <mode> <adc_printout>
   config_file_name  - name of file with FADC parametes
   mode              - FADC run mode, mode=0 external signals; mode>0 - playback (number triggers=mode) (overrides 'mode' from config file)
   adc_printout      >0 print out adc data block; =0 - no printout adc data block
Examples:
load FADC parrameters from file "config_1.fadc", external inputs, print adc data block:
>  ./famFadcTest config_1.fadc 0 1
redirection of printout to file for analysis: 
>  ./famFadcTest config_1.fadc 0 1 > fadc.dat

Simple ROOT ADC plot

Extract ADC data from printout file
> adc_print.sh fadc.dat > adc0.dat
Setup root:
> setenv ROOTSYS /apps/root/PRO
> setenv PATH /apps/root/PRO/bin:${PATH}
or
> source setup_root.sh
Plot ADC data in ROOT:
> root
root[] .x adc_read.C("adc0.dat",16)
Script to readout FADC and plot data in Root
Parameters are the same as for 'famFadcTEST' program:
> ./start_test.sh <config_file> <PB_MODE> <ADC_PRINT>
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