Log entry time 19:37:27 on October 05, 2011

Entry number 359292

This entry is a followup to: 359283

Ryan, Pengjia and I worked on the CODA configuration with the Intel CPU
for ROC 1 as ROC 8.  We first were able to successfully take data with 
only ROC 2 and the TS by creating a new configuration and setting the 
hardware ROCs appropriately.  

We then tried to run with RightIntel configuration.  However CODA was
not forming any events due to ROC 8 (ROC 1) not seeing any events.  I 
looked at the readout list and found that the following flag was 
incorrectly set for the TS control:

/* SFI_MODE:  0 : interrupt on trigger,
              1 : interrupt from Trigger Supervisor signal
              2 : polling for trigger
              3 : polling for Trigger Supervisor signal  */
#define SFI_MODE 1

We changed the value from 0 to 1, which fixed the no event problem, but
then we saw the following error messages in the ROC 8 window:

Sparse Data scan indicates no Conversion after 20 tries
Sparse Data scan indicates no Conversion after 20 tries

Also each event in xcefdmp did not even have a button for ROC 8 data.

Again looking closer at the readout list, the TDCs were being set to 
enable the COM signal from the front panel.  I commented out this line,
so that the stop is expected from the back panel:

tdc1877DisableFrontPanelCOM(slot+islot); /* enable COM from SD */
/*tdc1877EnableFrontPanelCOM(slot+islot);*/ /* disable COM from SD */

The above error messages went away and the ROC 8 button for each event 
now appears, but there is still no data in ROC 8.  We decided to stop for
today, and we will have to go through the new Intel readout list to find
out why no data is being written out for ROC 8 (ROC 1).