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    User name miham

    Log entry time 02:55:36 on April 24, 2009

    Entry number 267729

    This entry is a followup to: 267428

    keyword=BigBite Trigger and Re-timing

    Today during the day Bryan and myself were working on the BigBite trigger
    in order to resolve the issues from Wednesday. In particular, we
    were reorganizing the logic for the triggers T1,T2,T3 T5 and T6. We have
    removed ECL Prog. fan-out module and some additional logic from the T3
    trigger that were meant for the coincidence triggers. These changes
    bought us approximately 40ns of extra time i.e. Trigger T3 comes now 40ns
    earlier to the TS than did yesterday.

    Since T3 comes so late now, we had to introduce additional delay into the
    bigbite triggers T1 and T2. We have delayed T1 for approx. 60ns and T2
    for approximately 120ns. In the current setting T1 and T2 come at the
    same time to the TS and few ns after the T3.

    Because of so little spare time that we have available between the T3 and
    the analog signal to the ADCs we now can not build a very robust
    coincidence trigger. However, we made a simple approximation. Since T1 or
    T2 come right after T3, we have used a 755 module to create a wide gate
    (100ns) out of T3 and than "and"-ed this signal with T1 or T2. This
    should work as a simple coincidence trigger. Because we have added only
    one logical module (755) into the chain, the coincidence trigger should
    come to the TS only 8ns after T1 or T2 (it is timed of these two
    triggers),but we weren't able to test it properly yet.

    We also had to rebuild the BigBite re-timing. Now it is done in the
    following way: If there are T1 or T2 triggers available in the given
    event, than the L1A signal from TS should always be timed-off the T1. If
    there is only T2, is the L1A timed-off T2. If there is no T1 nor T2, than
    we use the delayed L1A (80ns) for the ADC gate and TDC common stop. In
    the case of a T1 event, the ADC gate comes approx 25-30ns before the
    analog pulse. In the case of T2 event, the gate comes 20-25 ns before
    the pulse. If the ADC gate is formed out of the delayed L1A pulse than
    the majority of the analog pulses misses the ADC window (because of the
    80ns shift).



    A copy of this log entry has been emailed to: moffit, sirca, miham