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    User name R. Michaels

    Log entry time 06:20:59 on September 16, 2009

    Entry number 289846

    This entry is a followup to: 289817

    keyword=re: CH scaler

    Three other issues I forget to mention about the CH scaler:

    1. The VME1 signal was inverted (wrong polarity). Flipping this made the part of the circuit
    work which ANDs this VME to the logic level from the 3rd bit of the TIR to make the LNE. It
    also changes the timing of all our gates by 2.5 usec which I think is negligible.

    2. Top 16 channels were unplugged. Cable hanging in front of V2F.

    3. 32nd channel was not a clock. We flipped the switch on the V2F to "16th = 4 MHz clock"
    so that the 32nd channel becomes a 4 MHz clock. Otherwise the calibrated scalers were all
    zero in Pan. Could fix this another way (force Pan to use 1.0 for calibration factor or use the
    raw scaler data instread) but decided to use the clock instead, as is standard.

    Yes, things had been messed up on this scaler. But the unit itself is probably ok.