Log entry time 11:52:17 on October16,2009

Entry number 295207

This entry is a followup to: 295072

Posted below are sync signals from the R-HRS and the CH scalers.

Remember, the sync signal is produced by a random variation of a 12-bit DAC 
which goes through a V-F and then gets gated and read out by a scaler.

The first Figure shows these plots for when the signal is split via  
T-connector in order to use the same 12-bit DAC signal for an ADC sync into a 
Voltage ADC. For some reason, the signal changes and drifts a little. 
Nonetheless, the sync check (bottom right) is what we would expect.

The second Figure shows plots after getting rid of the T-connector split. The 
signals are now perfectly linear as they should be. The sync check plot (bottom 
right) is what we expect.

So, even though the signal changes, the sync check is good for both instances.