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    User name Ramesh/Diancheng/Bob

    Log entry time 18:03:47 on November 08, 2009

    Entry number 298382

    This entry is a followup to: 298368

    keyword=Scaler gate and pion veto in RHRS

    As Bob mentioned in the earlier entry, during the controlled access we
    just plugged back in the unplugged ECL signal for scaler veto that goes
    to the 4th control channel of Happex and PVDIS scalers. In addition, we
    also plugged in Pion Veto signal in ch12 of NIM-ECL module6 (which used
    to have MPS signal for no reason). While potting histograms for pvdis
    fastbus TDC signal for Pion Veto, we need to understand that
    R.pv.t_cor[91] would be the correct histogram to plot.