Log entry time 11:06:28 on May 11, 2011

Entry number 358927

This entry is a followup to: 358826

I plot TDC spectra of S1 & S2m, for x>2 data (Figure 1):

 Run#3565: First x>2 production run.
 Run#3666: production run taken at the middle of x>2.
 Run#4275: production run taken at the last day of x>2.

The peaks values agree with timing spectra of current SRC data and had
shifts comparing with previous SRC data taken in April.

Since we used front panel to provide ADC gates, gates signals actually
comes a little big later than TDC STOP because those signals are passing
several modules and are splited into 5 pieces before they sent into fast
bus ADC front panels. 

I verified the ADC gate on RHRS at the beginning of x>2 experiment and
even if the ~60ns shift is real after I verified the gates, we still have
270ns width of the gates, so I believe the wide gate should be enough to
integrate all ADC signal. Figure 2 and Figure 3 are plots of S1 ADC and
Cer_Sum for old SRC data(3397) and new SRC data(4315),of which timing has
been shifted. You can see that ADC has no much difference. 

Figure 1

Figure 2

Figure 3