DVCS DAQ HRS setup

HRS DAQ info

[Portserver assignements]

 boot device          : dc
 unit number          : 0 
 processor number     : 0 
 host name            : adaql2
 file name            : /adaqfs/halla/a-onl/vxworks/5.4/vx2400
 inet on ethernet (e) : 129.57.192.25:ffffff00
 host inet (h)        : 129.57.164.59
 gateway inet (g)     : 129.57.192.1
 user (u)             : adev
 flags (f)            : 0x20 
 target name (tn)     : hallasfi3
 startup script (s)   : /adaqfs/halla/a-onl/vxworks/sfi3.boot

 boot device          : fei
 unit number          : 0 
 processor number     : 0 
 host name            : adaql2
 file name            : /adaqfs/home/a-onl/vxworks/kernels/5.5/vx5100
 inet on ethernet (e) : 129.57.192.26:ffffff00
 host inet (h)        : 129.57.164.59
 gateway inet (g)     : 129.57.192.1
 user (u)             : adev
 flags (f)            : 0x20 
 target name (tn)     : hallasfi4
 startup script (s)   : /adaqfs/halla/a-onl/vxworks/sfi4_5.5.boot

 boot device          : fei
 unit number          : 0 
 processor number     : 0 
 host name            : adaql2
 file name            : /adaqfs/halla/a-onl/vxworks/5.5/vx5100_v2
 inet on ethernet (e) : 129.57.192.30:ffffff00
 host inet (h)        : 129.57.164.59
 gateway inet (g)     : 129.57.192.1
 user (u)             : adev
 flags (f)            : 0x20 
 target name (tn)     : hallavme4
 startup script (s)   : /adaqfs/halla/a-onl/vxworks/vme_left.boot

Crates

HRS crates

• ROC3 fastbus hallasfi3 portserver hatsv4 2002

• ROC 4 fastbus hallasfi4 portserver hatsv40 2005

• TS11 VME hallavme4 portserver hatsv4 2007

DVCS DAQ info

VME crates

• ROC 18 VME crate dvcstlab6
  • TI 0x0ed0 ROC ID 5 portserver hatsv40 2004 crate ps hatsv40 2003
  • ARS 59247A
• ROC 17 VME crate dvcstlab4
  • TI 0x0ed0 ROC ID 0 portserver dvcstlab1 2002
  • ARS 163 12 8
  • Trigger interface 0x1e
• ROC 14 VME crate hallavme4
  • TI 0x0ed0 ROC ID 4
  • ARS 0xe 0xd 0xf

FPGA

http://www.jlab.org/~adaq/halog/html/1010_archive/101011190234.html http://www.jlab.org/~adaq/halog/html/1010_archive/101012004022.html

• USB0 47a top crate
• USB1 592 top crate
• USB2 12 8 1 E middle crate
  • First FPGA is board 0x1e
  • Second FPGA is board 0x8
  • Third FPGA is Trigger 0x12

• USB3 bottom crate 0edf
• pvdis3 163 middle crate
• hablaster2 trigger

DVCS library functions

ARSWriteRegister ( long int baseaddress, long int offset ,long int value )

long int ARSReadRegister ( long int baseaddress, long int offset )

void ReadReg(int maxreg, long int baseaddress )

ARSInit ( long int boardadd )

ARSInitText ( long int boardadd , const char * param)

int CalcValue( int n0, int n1, int n2, int n3)

ARSInitDacA(long int baseaddress, int a0,int a1,int a2,int a3)//initialization for DAC A

ARSInitDacB(long int baseaddress, int a0,int a1,int a2,int a3)//initialization for DAC B

ARSInitDacC(long int baseaddress, int a0,int a1,int a2,int a3)//initialization for DAC C

ARSInitDacD(long int baseaddress, int a0,int a1,int a2,int a3)//initialization for DAC D

ReadFile ( const char fname[255],int baseaddress)

int Dacodac(int baseaddress, int N,int a0,int a1,int a2,int a3)

void LitN(long int baseaddress,int N)

void ReadFifoMBLTOld(long int baseaddress)

void ReadFifoMBLTOldHalf(long int baseaddress)

void ReadFifoWord(long int baseaddress)

void AlignARS(long int baseaddress)

void AlignARSSimple(long int baseaddress)

void AlignAllARS()

void ReadAllARSWord()

void ReadFifoMBLT(long int baseaddress)

int GetOffset()

int GetCard(const char fname[255])

int GetOffset2(const char fname[255])

void ARSResetFan()

void GenerateT5()

void TriggerEvent()

MasterReset(const char fname[255])

ReadALLFile( const char fname[255],int baseaddress)

BigInit(const char fname[255])

afficher()

ARSBoardFill(const char fname[255])

FreeFifo()

int NbFifo(long int boardadd)

void NbFifoAll()

void DispWordAll()

int carlos(long int boardadd)

int NbFifo2(long int boardadd)

int EmptyFifo()

int VerifInit(long int boardadd)

void DispOneCol()

void DispTwoCol()

void InitTestBench(short int frequencymsb, short int frequencylsb,short int widthD, short int widthE, short int trigI)

void SetCaloChannelText(const char * name )

Useful commands=

dp_ask ROC18 download ROC18only

DP_ask ROC14 download ROC14only

DP_ask ROC17 download ROC17only

DP_ask ROC17 exec "DispWordAll()"

DP_ask ROC14 exec "DispWordAll()"

DP_ask ROC18 exec "DispWordAll()"

Scaler channels assignement

0 T1 S2m

1 T2 S0

2 T3 (S1 and S2)

3 T4 Efficiency

4 T5 DVCS trigger

5 T6 ARS Stop

6 T7 Led trigger

7 1024 Hz clock

8 DVCS-clk ????

9 HRS singles S2 cerkenkov

10 Singles-or : Or HRS with clock input or cosmics input

11 Master or : Singles or + coincidences

12 TS Accept

13 edtm

14 Electron trig : all triggers to generate validation

15 Pion trigger : subset of previous with anti cerenkov

16 bcm u10

17 bcm u3

18 bcm u1

19 bcm d10

20 bcm d3

21 bcm d1

22

23 Clock 1024 Hz

24 Clock 104 KHz

25

26

27

28

29

30

31

LED settings

Delay

fa500068: 0069- fa50006a: 0000-

Library

Sync signals

http://www.jlab.org/~adaq/halog/html/1010_archive/101005121528.html

ADC synch checker cables are installed: one cable is connected to Crate 3: slot 23: channel 48 another is connected to Crate 4: slot 24: channel 48 The other two suppose to go to the ARS (not connected yet)

=ARS related information

ARS additionnal information decoding

ARS initial documentation

Crates

Slot	Board address
0	VME CPU
1	TI
2
3
4
5
6
7
8
9
10
11
12
12
12
13
14
15
16
17
18
19
20
21