June 1st 2024

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Subsystem updates

https://redmine.jlab.org/projects/sbs-daq-gep?jump=welcome

https://redmine.jlab.org/projects/sbs-daq-gep/issues

  • ECAL
    • BigBite being uncabled
    • are distances optimizaed for calibration ? HIgh Q2 for fully popoulated, low Q2 could go closer, need to be checked ?
  • HCAL
    • need better calibration procedure and HV setting
    • might want to run at higher gain
    • digital trigger should be better since coefficient can be included
    • noisy PMTS , at limit
    • possible loss of efficiency for GEn, GEn RP
    • 1 to 3 MHz HCAL trigger during experiments
    • keep analog trigger for cross
    • no plan for change of PMTs during down
    • check problematic channels for Gep : noise
    • add amplifiers on channel with low gain ?
    • LED ? Useful for PMT characterization
    • MIP HCAL calibration ?
    • GEp Hydrogen scattering : recasterring and energy loss in analyzer - HCAL at 10 meters
    • recommended HV channel during GEn RP : some HV might have been highers that needed to be - edge can be manually tweaked -
  • CDet
    • focusing on what is needed to get detector ready to put in hall and put together : cables , infrastructure
    • need to think about calibration
    • set up VETROC
    • need help with cable setup : check in hall
    • need ribbon cables from detector to patch
    • ribbon cable from repeater to VETROC crate length
    • SHV feed through and patch panel ordered
    • test of power supply for NINON : voltage drop from patch panel - with length planned in the hall
    • VETROC adapter : connector give
    • spreadsheet for cables availbale, will put link in wiki
    • Peter, Rakph, SULI student, Andrew Master student
    • VETROC software : send email to Ed Brash about software
    • gain matching , discriminator threshold need to be calibratied quickly at beginning
    • threshold set on NINO with potentiometer -
    • TDC and TOT : for amplitude calibration
    • PMT gain curves ? Have all of them but the last one
    • FADC ? - not planned to have signals -
    • plan for a few analog cables for FADC - maybe 64 to 100


  • Trigger
    • lookup tables for trigger, Kipp has already look up tables for FPGA implementation
  • GEMs
    • lookup tables for GEMs
    • GEM configuration not finalized yet
    • pixel readout
    • check with Nilanga and simulation people Eric, Kipp
    • DAQ modes : full readout, with supression, with ROI
    • selective readout : MPD level or VTP level -