Difference between revisions of "FADC DAQ"
From Hall A Wiki
(→Known Issues and Firmware upgrade) |
(→Known Issues and Firmware upgrade) |
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*[http://hallaweb.jlab.org/equipment/moller/fadc/updates/fadc_upgrade.html Known FADC issues]* | *[http://hallaweb.jlab.org/equipment/moller/fadc/updates/fadc_upgrade.html Known FADC issues]* | ||
* Plan for upgrade | * Plan for upgrade | ||
| − | + | * FADC firmware upgrading | |
| − | + | We considering the possibility to have more counters array and programable logic | |
unit (PLU) on the board of FADC to programming a single channel coincidence | unit (PLU) on the board of FADC to programming a single channel coincidence | ||
and counting it on the scalers. | and counting it on the scalers. | ||
| Line 97: | Line 97: | ||
The module type of LeCroy-2365 can be used as prototype for this PLU. | The module type of LeCroy-2365 can be used as prototype for this PLU. | ||
| − | + | * Preliminary PLU parameters: | |
16 inputs by 16 outputs, with possibility to provide the connection | 16 inputs by 16 outputs, with possibility to provide the connection | ||
| Line 103: | Line 103: | ||
(OR), (AND) for inputs and function (NOT) for outputs. | (OR), (AND) for inputs and function (NOT) for outputs. | ||
| − | + | * The programmable registers(read/write): | |
16 registers ( 16bit) for AND function (every bit is corresponded to one input, | 16 registers ( 16bit) for AND function (every bit is corresponded to one input, | ||
| Line 111: | Line 111: | ||
one (16bit) register for NOT function of output (every bit is corresponded to one output). | one (16bit) register for NOT function of output (every bit is corresponded to one output). | ||
| − | + | * Scalers array: | |
16 channel of 32bit counters connected to the corresponded outputs of the PLU. | 16 channel of 32bit counters connected to the corresponded outputs of the PLU. | ||
| − | + | * Add the possibility to disable generation of "Data trigger" at all and enable only trigger from helicity. | |
= Literature= | = Literature= | ||
Revision as of 13:14, 22 November 2016
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Original_Moller_FADC_page(fadc)
Contents
Documentation
DAQ
- VME Crate Diagram
- VME Crate Modules
- FlexIO Board
- Scaler Module V560 (pdf)
- CAEN QDC V792 (pdf)
- Connection Diagram
- Signal Connections
FADC Documentation
- Hardware Architecture (pdf presentation)
- Firmware Architecture part1 (pdf)
- Firmware Architecture part2 (pdf)
- Data Format (pdf)
CODA Startup
- FADC CODA is running on hamoller computer under moller account.
To start CODA one can type command: start_coda_fadc - that fires up the usual set of windows for ET, ER, EB, etc. For FADC DAQ fadc_moller configuration in CODA RunControl is used.
- FADC parameters.
There is configuration file with settable parameters for FADC. File is located in directory: ~moller/crl/FADC/fadc_params.cnf Parameters from file are loaded to FADC in Prestart state of CODA.
There is self explained list of FADC parameters from configuration file:
# Wed Apr 21 16:22:20 EDT 2010 # FADC settable parameters
# Threshold on calorimeter sums (define triggers and SW scaler logic) FA_SUM_THRESH_CR 8500 FA_SUM_THRESH_CL 8500
# Threshold on individual channels # Define SW scaler logic for Scintillators only # Controls digitized data output for all channels (ie. 'zero-suppression') FA_CHN_THRESH_SR 500 FA_CHN_THRESH_SL 500 FA_CHN_THRESH_CR 500 FA_CHN_THRESH_CL 500
## Prescale range: 1--2047 FADC_PRESCALE_CL 1000 FADC_PRESCALE_CR 1000 FADC_PRESCALE_CRL 200 ## These many DATA trigger are grouped into each DATA interrupt FADC_EVENTS_PER_BLOCK 20
## PULSE_WIDTH range is from 3--255 (3 is default) FADC_PULSE_WIDTH 3
## COIN_WIDTH range is from 1--255 (2 is default) FADC_COIN_WINDOW 2
## Delays range: 1--255 FADC_DELAY_CL 0 FADC_DELAY_CR 0 FADC_DELAY_SL_0 1 FADC_DELAY_SL_1 1 FADC_DELAY_SL_2 1 FADC_DELAY_SL_3 1 FADC_DELAY_SR_0 1 FADC_DELAY_SR_1 1 FADC_DELAY_SR_2 1 FADC_DELAY_SR_3 1 ## This delay is for the _delay counts (random background measure) FADC_DELAY_SRL 25
- Data stored on hamoller computer to directory: /data1/raw/
Analysis
- Start ROOT-based analizer
- Data Trigger Analysis
Useful tips
- Signal photos: MPS(blue) vs Helicity(yellow) signal, zoomed , as on Oct 07 2012
Known Issues and Firmware upgrade
- Known FADC issues*
- Plan for upgrade
- FADC firmware upgrading
We considering the possibility to have more counters array and programable logic unit (PLU) on the board of FADC to programming a single channel coincidence and counting it on the scalers.
For example:
sumLS.and.CL2.and.CR2,
sumLS.and.CL2.and.sumCR, ... and so on.
The module type of LeCroy-2365 can be used as prototype for this PLU.
- Preliminary PLU parameters:
16 inputs by 16 outputs, with possibility to provide the connection
of any inputs to any output through the logic function of
(OR), (AND) for inputs and function (NOT) for outputs.
- The programmable registers(read/write):
16 registers ( 16bit) for AND function (every bit is corresponded to one input,
the register number is corresponded to the output number),
16 registers ( 16bit) for OR function (every bit is corresponded to one input,
the register number is corresponded to the output number)
one (16bit) register for NOT function of output (every bit is corresponded to one output).
- Scalers array:
16 channel of 32bit counters connected to the corresponded outputs of the PLU.
- Add the possibility to disable generation of "Data trigger" at all and enable only trigger from helicity.
