Difference between revisions of "TDIS DAQ, June 6 2017"
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== Minutes== | == Minutes== | ||
* Thia's summary of the meeting | * Thia's summary of the meeting | ||
| + | June 6, 2017 | ||
| + | |||
| + | Paul King talked.. lots of questions presented for discussion… overview, some needs | ||
| + | |||
| + | We should set up a wiki page, and upload this talk | ||
| + | |||
| + | Slide 7 add question – how to handle pile-up? | ||
| + | |||
| + | Asked about DREAM chips… Kondo said not clearly better than APV25, and we should look at what else is on the market… he will do this for next time, there are indeed options on the market | ||
| + | '''Kondo will present next meeting''' | ||
| + | |||
| + | Think about how many chips we’ll need, how many channels (560), how many can we fit on a board (some discussion) | ||
| + | |||
| + | Graham - need to put chips a bit away from the rTPC (~0.5 meter), as BONUS is doing, maybe need to design also shielding | ||
| + | |||
| + | Graham – what about data volume? Chris, max readout of 25 MHz (DREAM spec)… Paul calculated ~25 Mbyte/sec/chip, 12 bit adc from Gabriel’s BONUS/TDIS talk | ||
| + | |||
| + | How many events/sec? | ||
| + | |||
| + | Graham - sPHENIX reads out continuously, the trigger then gives a time window (different approach), a flash adc on steroids – use ALICE chips, but could also likely work with DREAM – clock them – look at time windows and throw away what’s not needed before writing to tape | ||
| + | |||
| + | How many total channels? 36,000 pads | ||
| + | Know hits/pad/sec | ||
| + | So, know hits/detector/sec | ||
| + | FIGURE out the data rate! GByte OK if not stored to tape (per above) | ||
| + | '''Paul to present next meeting''' | ||
| + | |||
| + | How to route out the cables/traces – can post Nilanga’s design | ||
Revision as of 13:07, 12 July 2017
Back to Tagged DIS run group >> DAQ development Meetings
previous meeting << >> following meeting
Agenda
- Discussion of Paul's notes
Minutes
- Thia's summary of the meeting
June 6, 2017 Paul King talked.. lots of questions presented for discussion… overview, some needs We should set up a wiki page, and upload this talk Slide 7 add question – how to handle pile-up? Asked about DREAM chips… Kondo said not clearly better than APV25, and we should look at what else is on the market… he will do this for next time, there are indeed options on the market Kondo will present next meeting
Think about how many chips we’ll need, how many channels (560), how many can we fit on a board (some discussion) Graham - need to put chips a bit away from the rTPC (~0.5 meter), as BONUS is doing, maybe need to design also shielding Graham – what about data volume? Chris, max readout of 25 MHz (DREAM spec)… Paul calculated ~25 Mbyte/sec/chip, 12 bit adc from Gabriel’s BONUS/TDIS talk How many events/sec? Graham - sPHENIX reads out continuously, the trigger then gives a time window (different approach), a flash adc on steroids – use ALICE chips, but could also likely work with DREAM – clock them – look at time windows and throw away what’s not needed before writing to tape How many total channels? 36,000 pads Know hits/pad/sec So, know hits/detector/sec FIGURE out the data rate! GByte OK if not stored to tape (per above) Paul to present next meeting How to route out the cables/traces – can post Nilanga’s design
