FADC DAQ
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Original_Moller_FADC_page(fadc)
Contents
Documentation
DAQ
- VME Crate Diagram
- VME Crate Modules
- FlexIO Board
- Scaler Module V560 (pdf)
- CAEN QDC V792 (pdf)
- Connection Diagram
- Signal Connections
FADC Documentation
- Hardware Architecture (pdf presentation)
- Firmware Architecture part1 (pdf)
- Firmware Architecture part2 (pdf)
- Data Format (pdf)
CODA Startup
- FADC CODA is running on hamoller computer under moller account.
To start CODA one can type command: start_coda_fadc - that fires up the usual set of windows for ET, ER, EB, etc. For FADC DAQ fadc_moller configuration in CODA RunControl is used.
- FADC parameters.
There is configuration file with settable parameters for FADC. File is located in directory: ~moller/crl/FADC/fadc_params.cnf Parameters from file are loaded to FADC in Prestart state of CODA.
There is self explained list of FADC parameters from configuration file:
# Wed Apr 21 16:22:20 EDT 2010 # FADC settable parameters
# Threshold on calorimeter sums (define triggers and SW scaler logic) FA_SUM_THRESH_CR 8500 FA_SUM_THRESH_CL 8500
# Threshold on individual channels # Define SW scaler logic for Scintillators only # Controls digitized data output for all channels (ie. 'zero-suppression') FA_CHN_THRESH_SR 500 FA_CHN_THRESH_SL 500 FA_CHN_THRESH_CR 500 FA_CHN_THRESH_CL 500
## Prescale range: 1--2047 FADC_PRESCALE_CL 1000 FADC_PRESCALE_CR 1000 FADC_PRESCALE_CRL 200 ## These many DATA trigger are grouped into each DATA interrupt FADC_EVENTS_PER_BLOCK 20
## PULSE_WIDTH range is from 3--255 (3 is default) FADC_PULSE_WIDTH 3
## COIN_WIDTH range is from 1--255 (2 is default) FADC_COIN_WINDOW 2
## Delays range: 1--255 FADC_DELAY_CL 0 FADC_DELAY_CR 0 FADC_DELAY_SL_0 1 FADC_DELAY_SL_1 1 FADC_DELAY_SL_2 1 FADC_DELAY_SL_3 1 FADC_DELAY_SR_0 1 FADC_DELAY_SR_1 1 FADC_DELAY_SR_2 1 FADC_DELAY_SR_3 1 ## This delay is for the _delay counts (random background measure) FADC_DELAY_SRL 25
- Data stored on hamoller computer to directory: /data1/raw/
Analysis
- Start ROOT-based analizer
- Login to hamoller using moller account and type commands:
cd fadc_analysis/moller_fadc-17Dec2015/ bash source root-setup.sh cd onlana analyzer
- To replay data from coda file and create root file type in analyzer (run_number=3475):
.x replay_test.C(3475) This command will create moller_fadc_03475.root root file in directory: /data1/ROOTFILES/moller/
- To do analysis of all data from one root file type in analyzer (run_number=3475, number_events=-1 (all)):
.x do_analyze.C(3475, -1) This command loads file with parameters for analysis: analyzer_config.set and create root file with results moller_analyzer_results_3475.root in directory: /data1/ROOTFILES/moller/analyzer_results/ # analyzer.config.set # Dec 12 2014 # Parameters for FADC analyzer # use symbol '#' at begin of line for comments # --------------------------------------------
# number of events to analyze, -1 to all #max_event -1
# Our system requires the delayed helicity train be shifted by this number of MPS trigs ## dealy=0 window HEL_SHIFT 2
# Clock timer generator freqency (Hz) CLOCKHZ 100000
# software thresholds for FADC data trigger analysis THRESHOLD_CL 1300 THRESHOLD_CR 1300
# factor from old analyzer to calculate polarization # it depends from energy, pass, target, target position,... FACTOR 16.094
# Helicity window width in usec. (not precise). " HELTSTABLEd" in EPICS #HEL_GATE 971.65 HEL_GATE 33330
# Normalisation: 1 - clock, 2- beam charge (BCM) NORM 2
# Accidental subtraction: 1 - subtract, 0 - no subtraction ACCID_SUBTR 1
# BCM rates to current in uA coefficient for G2P BCM_to_I 1.
# BCM threshold current value for no beam in uA BCM_CUT 50.
# Processing Data Trigger: 1 - processing, 0- do not processing. PROCESS_DT 0
# number of warnings to print NO_WARNINGS 10
# number of errors to print NO_ERRORS 10
# window size for graphs CANVASX 1024 CANVASY 800
# if >0 print debug info DEBUG 0
# if >0 do not save results to root file NO_ROOT_FILE 0
- To plot table with results and histograms type ("run_list_3463-3470" - file with list of run numbers):
.x plot_results10.C("run_list_3463_3470")
- There are two scripts to do analysis in batch mode for list of runs:
b_replay.sh - creates root files from coda files b_analyze.sh - creates root files with results These scripts take as argument name of file with list of run numbers to analyze. do_run_list.sh - this script generates file with list of runs.
- To do analysis in batch mode:
# Generate file with list of run numbers (runs from 3470 to 3475): do_run_list.sh 3470 3475 will create file: /data1/ROOTFILES/moller/analyzer_results/run_list_3470_3475 # to replay: b_replay.sh /data1/ROOTFILES/moller/analyzer_results/run_list_3470_3475 # to analyze: b_analyze.sh /data1/ROOTFILES/moller/analyzer_results/run_list_3470_3475
Useful tips
- Signal photos: MPS(blue) vs Helicity(yellow) signal, zoomed , as on Oct 07 2012
Known Issues and Firmware upgrade
- FDAC deadtime ???:
The FADC _DATA_ triggers have an intrinsic 100--150ns associated deadtime. - We measure gap from 0 to 150ns in the Poisson distributed time-between-triggers for production data. Ed J. can account for 90--100ns of that as described below. We're not sure where the remaining 50ns is coming from, but I don't think we care at that level. The FADC scaler data (ie. HELicity triggers) do /not/ have this deadtime.
- FADC firmware upgrading
We considering the possibility to have more counters array and programable logic unit (PLU) on the board of FADC to programming a single channel coincidence and counting it on the scalers.
For example: sumLS.and.CL2.and.CR2, sumLS.and.CL2.and.sumCR, ... and so on.
The module type of LeCroy-2365 can be used as prototype for this PLU.
- Preliminary PLU parameters:
16 inputs by 8 outputs, with possibility to provide the connection of any inputs to any output through the logic function of (OR), (AND) for inputs and function (NOT) for outputs.
- The programmable registers array(read/write):
8 registers ( 16 bit) for AND function (every bit is corresponded to one input, the register number is corresponded to the output number), 8 registers ( 16 bit) for OR function (every bit is corresponded to one input, the register number is corresponded to the output number) one (8 bit) register for NOT function of output (every bit is corresponded to one output).
- Scalers array:
8 channel of 32bit counters connected to the corresponded outputs of the PLU.
- Add the possibility to disable generation of "Data trigger" at all and enable only trigger from helicity.