DVCS DAQ HRS setup

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Revision as of 01:31, 12 October 2010 by Camsonne (Talk | contribs) (FPGA)

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HRS DAQ info

[Portserver assignements]


Crates

HRS crates

  • ROC3 fastbus hallasfi3 portserver hatsv4 2002
  • ROC 4 fastbus hallasfi4 portserver hatsv40 2005
  • TS11 VME hallavme4 portserver hatsv4 2007

DVCS DAQ info

VME crates

  • ROC 18 VME crate dvcstlab6
    • TI 0x0ed0 ROC ID 5 portserver hatsv40 2004 crate ps hatsv40 2003
    • ARS 59247A
  • ROC 17 VME crate dvcstlab4
    • TI 0x0ed0 ROC ID 0 portserver dvcstlab1 2002
    • ARS 163 12 8
    • Trigger interface 0x1e
  • ROC 14 VME crate hallavme4
    • TI 0x0ed0 ROC ID 4
    • ARS 0xe 0xd 0xf

FPGA

http://www.jlab.org/~adaq/halog/html/1010_archive/101011190234.html http://www.jlab.org/~adaq/halog/html/1010_archive/101012004022.html

  • USB0 47a top crate
  • USB1 592 top crate
  • USB2 12 8 1 E middle crate
    • First FPGA is board 0x12
    • Second FPGA is board 0x8
    • Third FPGA is Trigger 0x1e
  • USB3 bottom crate 0edf
  • pvdis3 163 middle crate
  • hablaster2 trigger


DVCS library functions

Useful commands

DP_ask ROC17 exec "DispWordAll()"

DP_ask ROC14 exec "DispWordAll()"

DP_ask ROC18 exec "DispWordAll()"

=ARS related information

ARS additionnal information decoding

ARS initial documentation


Slot Board address
0 VME CPU
1 TI
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